Intel’s first three generations of client processors implementing hybrid CPU cores, namely “Alder Lake,” “Raptor Lake,” and “Meteor Lake,” have them arranged along a ringbus, sharing an L3 cache. This usually sees the larger P-cores to one region of the die, and the E-core clusters to the other region. From the perspective of the bidirectional ringbus, the ring-stops would follow the order: one half of the P-cores, one half of the E-core clusters, iGPU, the other half of E-cores, the other half of the P-cores, and the Uncore, as shown in the “Raptor Lake” die-shot, below. Intel plans to rearrange the P-cores and E-core clusters in “Arrow Lake-S.”
With “Arrow Lake,” Intel plans to disperse the E-core clusters between the P-cores. This would see a P-core followed by an E-core cluster, followed by two P-cores, and then another E-core cluster, then a lone P-core, and a repeat of this pattern. Kepler_L2 illustrated what “Raptor Lake” would have looked like, had Intel applied this arrangement on it. Dispersing the E-core clusters among the P-cores has two possible advantages. For one, the average latency between a P-core ring-stop and an E-core cluster ring-stop would reduce; and secondly, there will also be certain thermal advantages, particularly when gaming, as it reduces the concentration of heat in a region of the die.